• 社会招聘
    1. 长沙总部
    2. 成都地区
    3. 上海地区
    4. 北京地区
    5. 常州地区
    6. 台湾地区
    7. 美国
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    台湾地区

  • 招聘岗位

    1. 市场经理-SSD

    工作地: 成都或新竹

    招聘人数: 1

    · 岗位职责: 

    負責SSD或HDD或flash memory controller 產品市場規劃,專案管理,與導入量產。

    · 岗位要求:

    1. 3年以上SSD / NAND Flash相關電子業專案管理或開發經驗;

    2.具IC設計公司PM經驗者尤佳;

    3.具SSD,Flash Memory或工業電腦產業領域,或封裝測試工作經驗者尤佳;

    4. 熟悉產品開發驗證流程;

    5. 英文達到可和客戶工作上流暢溝通;

    6. 可接受出差或短期派駐;

    7.可快速判定問題優先順序,並可協同RD用作,達到高效問題定位以及解決能力;

    8.具OEM vendor / partner管理經驗者佳。

     

    2. SE(系统工程师)-ISP

    工作地: 成都或新竹

    招聘人数: 1

    · 岗位职责: 

    1. 负责ISP IP路标规划及设计架构实现;

    2. 研究并实现下一代ISP算法,包括但不限于降噪(2D/3D),去马赛克,3A,HDR等;

    3. 负责ISP IP规格定义,和数字设计团队共同完成IP设计和验证任务;

    4. 负责ISP SDK/工具开发;

    5. 负责ISP FPGA验证及图像调优。

    · 岗位要求:

    1. 5年以上ISP或成像系统设计经验;

    2. 在图像处理领域具有深厚的理论功底;

    3. 精通图像处理相关开发工具,例如Matlab/C;

    4. 具有RTL相关芯片设计经验;

    5. 计算机科学,数学及相关专业,硕士及以上学位。

     

    3. SE(系统工程师)-芯片

    工作地: 长沙或成都或新竹

    招聘人数: 1

    · 岗位职责: 

    1、梳理STB芯片需求,确定规格,完成Soc系统评估,确定芯片架构设计方案;

    2、审查数字电路设计,验证,综合及时序分析环节;

    3、审查相关设计文档的输出;

    4、协助芯片验证,debug,配合其他部门一起完成芯片方案开发,量产测试等相关工作;

    5、重度参与芯片路标规划。

    · 岗位要求:

    1、本科及以上学历,8年以上数字设计工作经验,多次成功Tape out经验;

    2、熟练使用Verilog语言,有一定的shell、TCL、Perl以及常用EDA软件使用经验;

    3、熟悉Arm处理器Soc架构,熟悉总线,DDR以及其他常用外设接口;

    4、熟悉芯片开发前后端流程,熟悉性能,功耗及成本评估;

    5、具备图像处理,视频编解码经验者,或者具有相关Soc架构设计经验者优先。

     

    4. Principle Engineer,DDR Controller and PHY SOC Design

    工作地: 新竹或美国

    招聘人数: 1

    · Responsibilities:

    – RTL Design and implementation of interface logic between DDR controller and DMA engines for high performance networking application

    – Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals

    – Review vendor IP integration guidelines and verify the compliance throughout the design flow

    – Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines

    – Participate in design verification process by reviewing test plans, coverage reports, writing assertions

    and other design modifications to improve verification quality

    – Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals

    – Be able to work and communicate with multi-site teams

    – Responsible for the review of netlist releases (pre/post-route/eco, block/chip)

    · Experience/Skills:

    – Solid understanding of DDR architecture.  Must have implemented/verified DDR sub systems on recent technology nodes

    – Extensive experience in integration and validation of high speed DDR IP core (including controller and PHY SerDes)

    – Recent experience with DDR3, DDR4 protocols

    – Experience with SERDES protocol analyzers and silicon-debugging tools

    – 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency

    – Experience with multiple clock and power domains

    – Familiarity with ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

     

    5. Principle Engineer,PCIe Controller and PHY SOC Design

    工作地: 新竹或美国

    招聘人数: 1

    · Responsibilities:

    – RTL Design and implementation of interface logic between PCIe controller and DMA engines for high performance networking application

    – Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals

    – Review vendor IP integration guidelines and verify the compliance throughout the design flow

    – Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines

    – Participate in design verification process by reviewing test plans, coverage reports, writing assertions

    and other design modifications to improve verification quality

    – Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals

    – Be able to work and communicate with multi-site teams

    – Responsible for the review of netlist releases (pre/post-route/eco, block/chip)

    · Experience/Skills:

    – Extensive experience in integration and validation of high speed PCIe IP core (including controller and PHY SerDes)

    – Recent experience with PCIe Gen3 and Gen4 protocols

    – Experience with PCIe protocol analyzers and silicon-debugging tools

    – Familiarity with PCIe driver and application software for Linux/Windows

    – 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency

    – Experience with multiple clock and power domains

    – Familiarity with ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)

     

    6. 芯片验证工程师-SSD

    工作地: 成都或新竹

    招聘人数: 2

    · Responsibilities:

    –  Develop, and maintain UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference model.

    –  Perform verification of PCIe and NVMe interface and I/O using VIPs

    –  Perform verification of DMA engines and SOC-related datapath channels

    –  Perform verification of ECC and security modules against fixed-point cycle accurate C/C++ code

    · Experience/Skills:

    –  Minimum of 10 years of experience in ASIC SOC designs.

    –  Develop, and maintain UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference model.

    – Strong experience in SSD controller H/W architecture & design .

    –  Strong Experience in RTL design, design verification synthesis & formality.

    –  Solid experience in PCIe & NVMe interfacing & understand the I/O protocols.

    –  Experience in DMA engines and network-no-chip architectures.

    –  In-depth knowledge of NAND Flash memories & their operation.

    –  Understand various ECC codes.  

    –  Support Design Verification & FPGA Validation, teams.

    –  Architect automation HW to improve the Data & Command throughput.

     

    7. 芯片验证副总监-SSD

    工作地: 新竹

    招聘人数: 1

    · Responsibilities:

    – Build, Grow and Lead SoC verification teams

    – Develop detailed plan for pre-silicon verification/validation

    – Review and enhance verification methodology and module-level/system-level verification

    – Work closely with ASIC design and software teams to drive day-to-day verification related activities

    · Experience/Skills:

    – Build, Grow and Lead SoC verification teams

    – Develop detailed plan for pre-silicon verification/validation

    – Review and enhance verification methodology and module-level/system-level verification

    – Work closely with ASIC design and software teams to drive day-to-day verification related activities

    – 10+ years of RTL verification experience and Verilog/System Verilog proficiency

    –  Must have experience with leading multiple chip verification project from start to production.

    –  Hands-on experience with RTL Verification & Debug tools.

    –  Experience with project management and tracking project from Specification to Verification Sign-off is must.

    –  Experience with FPGA and/or In-circuit emulation platforms such as Palladium/Veloce is plus.

    –  Must have good communication skills.

     

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